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AS5013
Datasheet - Detailed Description
7.5.2 I睠 Electrical Specification
Standard-mode, Fast-mode, High Speed-mode
Notes:
1. Maximum VIH = VDDpmax +0.5V or 5.5V, which ever is lower.
2. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50ns in Fast-mode and 10ns in HS-mode.
3. I/O pins of Fast-mode and Fast-mode plus devices must not obstruct the SDA and SCL lines if VDDp is switched off.
7.5.3 I睠 Timing
Symbol
Parameter
Condition
Min
Max
Unit
VIL
LOW-level input voltage
-0.5
0.3VDDp
V
VIH
HIGH-level input voltage
0.7VDDp
VDDp + 0.5
(see note 1)
V
V
hys
Hysteresis of Schmitt Trigger inputs
VDDp < 2V
0.1VDDp
V
VOL
LOW-level output voltage (open-drain or
open-collector) at 3mA sink current
VDDp < 2V
-
0.2VDDp
V
IOL
LOW-level output current
VOL = 0.4V
-
-
mA
ICS
Pull-up current of SCLH current source
SCLH output levels between
0.3VDDp and 0.7VDDp
3
12
mA
t
SP
Pulse width of spikes that must be
suppressed by the input filter
In HS-mode
-
10
(see note 2)
ns
In Fast-mode
50
(see note 2)
ns
I
i
Input current at each I/O Pin
Input voltage
between 0.1VDDp and 0.9VDDp
10
(see note 3)
礎
C
B
Total capacitive load for each bus line
-
400
pF
C
I/O
I/O capacitance (SDA, SCL)
-
10
pF
Symbol
Parameter
Condition
Fast-mode
HS-mode C
B
=100pF
HS-mode
C
B
=400pF
1
Unit
Min
Max
Min
Max
Min
Max
fSCLK
SCL clock Frequency
-
400
-
3400
-
1700
kHz
t
BUF
Bus Free Time; time
between STOP and
START Condition
500
-
500
-
500
-
ns
t
HD;STA
Hold Time; (Repeated)
START Condition
2
600
-
160
-
160
-
ns
t
LOW
LOW Period of SCL Clock
1300
-
160
-
320
-
ns
t
HIGH
HIGH Period of SCL Clock
600
-
60
-
120
-
ns
t
SU;STA
Setup Time for a
Repeated START
condition
600
-
160
-
160
-
ns
t
HD;DAT
Data Hold Time
3
0
900
0
70
0
150
ns
t
SU;DAT Data Setup Time
4
100
-
10
-
10
-
ns
t
rCL
Rise time of SCLH signal
External pull-up
source of 3mA
-
-
10
40
20
80
ns
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